This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits typically include circuitry to perform data access functions to assist with read operations. For instance, a Static Random Access Memory (SRAM) read may require a dual-rail, differential voltage read by a sense amplifier followed by a singled-ended latch. While it is desirable to reduce a physical mismatch of a sense amplifier, it is also desirable to optimize output of the sense amplifier or other effect that is systematic to the design. For instance, FIG. 1 shows an example of conventional sense amplifier circuitry 100 having a sense amplifier 110 and a latch 120 that are arranged to receive a dual-rail, differential voltage (B and B) and output a singled-ended voltage (out). In common practice, as shown in FIG. 1, a first sense amplifier output (sd) is typically coupled to an input of the single-ended latch 120. In some cases, this arrangement may optimize memory area; however, this arrangement may create a rather substantial systematic offset. Further, in common practice, as shown in FIG. 1, a second sense amplifier output (nsd) is typically left without any coupling or connection, which will create unbalanced capacitance output from the sense amplifier 110 and will not provide a similar coupling effect for nsd output when compared to sd output. As such, there exists a need for more effective sense amplifier circuitry that improves power, performance and area (PPA) of an integrated circuit.